1. Field of Use
The present invention relates to data processing systems and in particular to memory systems which include cache stores.
2. Prior Art
It is well known that it is important to ensure the validity of information read out from a memory system. In general, the requisite reliability has been achieved by the addition of error correction and detection (EDAC) circuits to such memory systems. In order to provide the same degree of reliability for the cache store when included as part of the memory system, the same type circuits are provided.
It has been found that the major disadvantage of such arrangements is the added complexity to the cache store resulting from the inclusion of such circuits. Another important disadvantage is the additional time to each cache store cycle to provide for detection and correction of errors in the information read out from the cache store.
Accordingly, it is a primary object of the present invention to provide an improved arrangement for detecting and correcting errors in a cache type memory system.
It is a further object of the present invention to provide a cache type memory system which requires a minimal amount of error and detection circuits for ensuring reliable operation.